UPD78F0138M5GBA-8EU View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD78F0138M5GBA-8EU' PDF : 415 Pages View PDF
CHAPTER 1 GENERAL
Table 1-4. Functional Outline of µPD78064Y Subseries
Part Number
Item
µPD78062Y
µPD78063Y
µPD78064Y
Internal ROM
memory
Mask ROM
16K bytes
24K bytes
32K bytes
High-speed RAM 512 bytes
1024 bytes
LCD display RAM 40 × 4 bits
Memory space
64K bytes
General-purpose register 8 bits × 8 × 4 banks
Minimum With main
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz)
instruction system clock
execution With subsystem 122 µs (at 32.768 kHz)
time
clock
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjustment, etc.
I/O port
• Total
: 57
(including pins multiplexed • CMOS input : 2
with segment signal output) • CMOS I/O : 55
A/D converter
8-bit resolution × 8 channels
LCD controller/driver
• Segment signal output : 40 max.
• Common signal output : 4 max.
• Bias
: 1/2 or 1/3 bias selectable
Serial interface
• 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel
• 3-wire serial I/O/UART mode selectable
: 1 channel
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Timer output
3 (14-bit PWM output: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)
Vectored Maskable
interrupt Non-maskable
source Software
Internal: 12, external: 6
Internal: 1
1
Test input
Internal: 1, external: 1
Supply voltage
VDD = 2.0 to 6.0 V
Package
• 100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness 1.45 mm)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm, resin thickness 1.4 mm)
• 100-pin plastic QFP (14 × 20 mm)
13
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