UPD78P058F View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD78P058F' PDF : 415 Pages View PDF
CHAPTER 1 GENERAL
Table 1-8. Functional Outline of µPD78098 Subseries (1/2)
Part Number
Item
µPD78094
µPD78095
µPD78096
µPD78098ANote 1 µPD78P098ANote 1, 2
Internal ROM
memory
Mask ROM
32K bytes
40K bytes
48K bytes
60K bytes
PROM
60K bytesNote 3
High-speed RAM 1024 bytes
Buffer RAM
32 bytes
Expansion RAM None
2048 bytes
2048 bytesNote 4
Memory space
64K bytes
General-purpose register 8 bits × 8 × 4 banks
Minimum With main
0.5 µs/1.0 µs/2.0 µs/4.0 µs/8.0 µs/16.0 (at 6.0 MHz)
instruction system clock
execution With subsystem 122 µs (at 32.768 kHz)
time
clock
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjustment, etc.
I/O port
• Total
: 69
• CMOS input
:2
• CMOS I/O
: 63
• N-ch open-drain I/O: 4
IEBus controller
Effective transfer rate: 3.9 kbps/17 kbps/26 kbps
A/D converter
8-bit resolution × 8 channels
D/A converter
8-bit resolution × 2 channels
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable
: 1 channel
• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel
• 3-wire serial I/O/UART mode selectable
: 1 channel
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Timer output
3 (14-bit PWM output: 1)
Clock output
15.6 kHz, 31.3 kHz, 62.5 kHz, 125 kHz, 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz, 4.0 MHz (with
main system clock of 6.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Notes 1. Under development
2. The µPD78P098A is the PROM model of the µPD78094, 78095, 78096, and 78098A.
3. The internal PROM capacity can be changed by using a memory size select register (IMS).
4. The internal expansion RAM can be changed by using an internal expansion RAM size select register
(IXS).
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