OSCIN
STATE1
AS
DS
R/WR
M/IO
OP/IN
OPERAND
ADDRESS
OPERAND
DATA
SYMBOL
t36a *
t36b *
t36c *
t36d *
t36e
t36f *
t36g *
t36h *
t36i
t36j *
t36k
t36l *
t36n
t36o *
t36p *
t36q
t36r *
t36s
t36t
t36u
Note:
*Guaranteed by test.
t36a
t36c
t36f
t36j
t36l
t36o
t36r
PARAMETER
OSCIN low to STATE1 high
OSCIN low to STATE1 low
OSCIN low to AS active
OSCIN high to AS inactive
OSCIN low to AS high Z
OSCIN low to DS inactive
OSCIN low to DS active
OSCIN high to DS inactive
OSCIN low to DS high Z
OSCIN low to R/WR active
OSCIN low to R/WR high Z
OSCIN low to M/IO high
OSCIN low to M/IO high Z
OSCIN low to OP/IN high
OSCIN high to OP/IN low
OSCIN low to OP/IN high Z
OSCIN low to address valid
OSCIN high to address invalid
Data setup time
Data hold time
t36b
t36d
t36g
t36h
t36e
t36i
t36k
t36n
t36p
ADDRESS
VALID
t36s
DATA
VALID
t36t
t36u
t36q
12 MHz
MIN MAX
0
42
0
39
0
51
0
50
--
50
0
54
0
37
0
50
--
50
0
54
--
50
0
53
--
50
0
54
0
71
--
53
0
57
--
55
0
--
34
--
16 MHz
MIN MAX
0
33
0
33
0
42
0
38
--
38
0
45
0
35
0
38
--
38
0
42
--
38
0
42
--
38
0
41
0
53
--
40
0
45
--
41
0
--
26
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 36. MEM Read Cycle
45