V350EPC-33REVA0 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V350EPC-33REVA0' PDF : 18 Pages View PDF
V350EPC
Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz
40MHz
# Symbol
Description
Notes Min Max Min Max Units
1 TC LCLK period
30
25
ns
2 TCH LCLK high time
1
12
11
ns
3 TCL LCLK low time
1
12
11
ns
4 TSU Synchronous input setup
2
7
6
ns
4a TSU Synchronous input setup (BLAST)
8
7
ns
4b TSU Synchronous input setup (W/R, BTERM)
4
4
ns
4c TSU Synchronous input setup (ADS/AS)
6
5
ns
4d
TSU
Synchronous input setup (address, data,
byte enables)
9
8
ns
4e
TSU
Synchronous input setup for read data
when in local bus master mode
5
5
ns
5 TH Synchronous input hold
6 TCOV LCLK to output valid delay
3
6a
TCOV
LCLK to output valid delay (address, data,
byte enable, parity)
2
2 ns
3 14 3 12 ns
3 15 3 14 ns
7 TCZO LCLK to output driving delay
8 TCOZ LCLK to high impedance delay
9 TRST Reset period when LRST used as input
3 15 3 14 ns
4
3 15 3 14 ns
16·TC
16·TC
ns
Copyright © 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
15
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