V350EPC-40REVA0 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V350EPC-40REVA0' PDF : 18 Pages View PDF
V350EPC
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 5%
3
TH Synchronous input hold from PCLK
4 TCOV PCLK to output valid delay
4a TCOV PCLK to output valid delay (REQ)
5 TCZO PCLK to output driving delay
6 TCOZ PCLK to high impedance delay
7 TRST Reset period when PRST used as input
Notes:
1. All PCI bus signals except those in 2a.
2. All PCI bus signals except those in 4a.
0
ns
2
3
11 ns
4
12 ns
4
11 ns
5
18 ns
16·TC
4.3 Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms
generated are shown in Figure 4.
Figure 4: Serial EEPROM Waveforms and Timings
START CONDITION
512 PCI BUS
CLOCKS
STOP CONDITION
SCL
SDA
256 PCI BUS
CLOCKS
256 PCI BUS
CLOCKS
Copyright © 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
17
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