V360EPC-33 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V360EPC-33' PDF : 18 Pages View PDF
V360EPC
Signal
LD[31:0]
ID[31:0]b
LA[31:2]
BE[3:0]
BWE[3:0]b
W/R
R/Wb
ADS
LREQb
READY
RDYc
HOLD
LBREQb
HOLDA
LBGRTb
LPAR[3:0]
BLAST
BURSTb
BTERM
ERRb
LINT
LRST
LCLK
MEMCLKb
Table 3: Signal Descriptions (cont’d)
Type
Local Bus Interface
R Description
I/O4
Z Local multiplexed address and data bus.
I/O4
Z Local address bus.
I/O4
Z Local bus byte enables.
I/O4
Z Read-Write strobe.
I/O4
Z Asserted low to indicate the beginning of a bus cycle.
I/O4
Z Local Bus data ready
O4
L
Local bus hold request: asserted by the chip to initiate a local bus
master cycle.
I
Local bus hold acknowledge.
I/O4
Z Local bus parity.
I/O4
Z Burst lastc. Burst requestb.
I/O4
Z Bus Time-out. Burst terminatec.
O4
H Local interrupt request.
I/O4 L/Z Local bus RESET signal.
I
Local bus clock.
Signal
SCL/LPERR
SDA
Type
O4
I/O4
Serial EEPROM Interface
R Description
X EEPROM clock. Local parity error.
X EEPROM data.
4
V360EPC Data Sheet Rev 1.2
Copyright © 1998, V3 Semiconductor Inc.
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