V360EPC-50REVA0 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V360EPC-50REVA0' PDF : 18 Pages View PDF
V360EPC
Table 15: Local Bus Timing Parameters for Vcc = 3.3 Volts +/- 5%
33MHz
# Symbol
Description
Notes Min Max Units
1 TC LCLK/MEMCLK period
2 TCH LCLK/MEMCLK high time
3 TCL LCLK/MEMCLK low time
4 TSU Synchronous input setup
4a
TSU
Synchronous input setup
(BLAST,BTERM)/(BURST, ERR)
30
ns
1
12
ns
1
12
ns
2
8
ns
9
ns
4b TSU Synchronous input setup (ADS/LREQ)
4c
TSU
Synchronous input setup (address, data,
byte enables)
7
ns
8
ns
4d
TSU
Synchronous input setup for read data
when in local bus master mode
7
ns
4e
TSU
Synchronous input setup for (READY, W/
R, HOLDA)/(RDY, R/W, LBGRT)
5
5 TH Synchronous input hold
6 TCOV LCLK/MEMCLK to output valid delay
6a
TCOV
LCLK/MEMCLK to output valid delay
(address, data, byte enable, parity)
3 ns
3
4 14 ns
4 16 ns
7 TCZO LCLK to output driving delay
8 TCOZ LCLK/MEMCLK to high impedance delay
9 TRST Reset period when LRST used as input
4 16 ns
4
4 16 ns
16·TC
ns
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 10%
# Symbol
Description
1
TC PCLK period
2
TSU Synchronous input setup to PCLK
2a TSU Synchronous input setup to PCLK (GNT)
3
TH Synchronous input hold from PCLK
4 TCOV PCLK to output valid delay
Notes
1
2
Min Max Units
30
ns
7
ns
10
ns
0
ns
3
11 ns
16
V360EPC Data Sheet Rev 1.2
Copyright © 1998, V3 Semiconductor Inc.
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