V826632B24S View Datasheet(PDF) - Mosel Vitelic Corporation
Part Name
Description
MFG CO.
'V826632B24S' PDF : 14 Pages View PDF
MOSEL VITELIC
V826632B24S
DDR SDRAM IDD SPEC TABLE
Symbol
C0(DDR333@CL=2.5) B1(DDR266@CL=2) B0(DDR266@CL=2.5) A1(DDR200@CL=2) Unit
Notes
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6 Normal
Low power
IDD7A
590
730
24
210
165
285
450
1030
985
950
24
15
1640
560
650
24
160
150
245
370
870
820
850
24
15
1380
560
650
24
160
150
245
370
870
820
850
24
15
1380
460
585
24
150
130
210
330
770
690
760
24
15
1200
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA Optional
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826632B24S Rev. 1.1 July 2002
9
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