V826664G24SXSG-A1 View Datasheet(PDF) - Mosel Vitelic Corporation
Part Name
Description
MFG CO.
'V826664G24SXSG-A1' PDF : 14 Pages View PDF
MOSEL VITELIC
V826664G24S
DDR SDRAM IDD SPEC TABLE
Symbol
C0
DDR333@CL=2.5
Typical
B1
DDR266@CL=2
Typical
IDD0
880
800
IDD1
1120
1000
IDD2P
450
380
IDD2F
365
360
IDD2Q
340
280
IDD3P
450
380
IDD3N
460
400
IDD4R
1360
1360
IDD4W
1680
1480
IDD5
1600
1480
IDD6 Normal
54
54
Low power
30
30
IDD7A
2800
2600
B0
DDR266@CL=2.5
Typical
800
1000
380
360
280
380
400
1360
1480
1480
54
30
2600
A1
DDR200@CL=2
Typical
640
800
260
320
240
260
320
1120
1200
1200
54
30
2120
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA Optional
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826664G24S Rev. 1.0 August 2002
9
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