V961PBC-33REVB2 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V961PBC-33REVB2' PDF : 16 Pages View PDF
V961PBC
Figure 5: Serial EEPROM Waveforms and Timings
START CONDITION
512 PCI BUS
CLOCKS
STOP CONDITION
SCL
SDA
256 PCI BUS
CLOCKS
256 PCI BUS
CLOCKS
5.0 Revision History
Table 16: Revision History
Revision
Number
Date
Comments and Changes
2.4
5/98 Data sheet update of B2-step values
2.3
10/96
Data Book revision.
1. In Table 3, changed “LPAR[3:0]” to “LPAR[3:0]”.
1. In Table 3, changed “PERR I/OD” to “PERR I/O”.
2.2
06/96 2. In Table 3, added “VCC“ and “GND” description.
3. In Table 13 and 14 , added min TCOV and min TCZO timing.
2.1
03/96
1. Updated timings to final B1-step values.
2. Simplified data sheet format.
Removed operational description (found in User’s Manual). Device related
changes:
1. LA5, LA4, LA3, LA2 pins added to pinout for V960PBC and V961PBC.
2.0
11/95 2. Changed references to PCI 2.0 to PCI 2.1 spec level compliance.
3. Updated timings to final B0-step values.
4. Added new TCZO timing.
5. Added test mode pin description.
Copyright © 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
15
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