V96BMC View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V96BMC' PDF : 14 Pages View PDF
V96BMC Rev.D
Table 11: Timing Parameters for V96BMC Vcc=5 Volts +/- 5% and Vcc3= 5 or
3.3 8Volts +/- 5%
tWEH Write Enable hold from RAS de-assertion
tLED PCLK to Latch Enable output delay
6
tTXHL1 PCLK to Buffer Control fall delay
7
tTXHL2 PCLK to Buffer Control fall delay (Mode 2 and
3 at TXA pin only)
1
3
1
3 ns
3 12 3 10 ns
3 13 3 11 ns
4 15 4 13 ns
tTXLH PCLK to Buffer Control rise delay
3 12 3 10 ns
tRFHL REFRESH synchronous assertion delay
3 13 3 11 ns
tRFLH REFRESH synchronous de-assertion delay
3 13 3 11 ns
tASU Address setup to ALE Falling
6
5
ns
tAH Address hold from ALE Falling
5
4
ns
NOTES:
1. Specified from PCLK falling edge.
2. tM = tC when T_MUX = 1; tM = 0.5 • tC when T_MUX = 0.
3. Maximum RAS pulse width depends on the number of burst access.
4. tN = 1.5 • tC when T_RAS = 0; tN = 2.5 • tC when T_RAS = 1.
5. tP = 2 • tC when T_RAS = 0; tP = 2 • tC when T_RAS = 1 and T_RP = 1;
tP = 3 • tC when T_RAS = 1 and T_RP = 0.
6. Rising delay is measured from PCLK falling edge, falling delay is measured from PCLK rising edge.
7. Except for Mode 2 and 3 at TXA pin.
8. In order to have 3.3 Volt DRAM interface Vcc3 pins must be connected to 3.3 Volt.
Vcc3 pins are: PIN # 91, 97, 103, 109, 57, 63, 69, 75, 81.
The power supply pins that must always be connected to 5V are Vcc.
Vcc pins are: PIN # 4, 47, 115.
Figure 3: Clock and Synchronous Signals
LOCAL CLOCK
INPUT SETUP/HOLD
OUTPUT FALLING DELAY
OUTPUT RISING DELAY
OUTPUT RISING DELAY
tC
tCH
tCL
tSU
tH
VALID
tLED, BHL, EHL, IHL
,
RFHL, TXHL1, TXHL2
tBLH, ELH, ILH, RFLH
TXLH
tLED
12
V96BMC Rev D Data Sheet Rev 3.2
Copyright © 1998, V3 Semiconductor Inc.
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