VG26S18165C View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG26S18165C' PDF : 27 Pages View PDF
VIS
VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70°C, VCC = + 3.3V ±10 %, VSS = 0V)
Parameter
Symbol
Test Conditions
Operating current
ICC1
RAS cycling
LCAS / UCAS cycling
tRC = min
Standby Current
ICC2 LVTTL interface
RAS, LCAS / UCAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS ≥ VCC -0.2V
Dout = High-Z
RAS- only refresh current
ICC3
RAS cycling
LCAS / UCAS = VIH
tRC = min
EDO page mode current
ICC4
tPC = min
VG26V(S)18165
-5
-6
Unit Notes
Min Max Min Max
- 160
- 145 mA 1, 2
-
2
-
2 mA
- 0.5
- 0.5 mA
- 160
- 145 mA 1, 2
- 90
- 80 mA 1, 3
CAS- before- RAS
refresh
current
Self- refresh current
ICC5
ICC6
tRC = min
RAS, LCAS / UCAS cycling
tRASS ≥ 100µs
- 160
- 145 mA 1, 2
- 300
- 300 µA
Input leakage current
ILI
0V ≤ Vin ≤ VCC + 0.3V
-5
5 -5
5 µA
Output leakage current
Output high Voltage
Output low voltage
ILO
0V ≤ Vout ≤ VCC + 0.3V
Dout = Disable
VOH
IOH = -2mA
VOL
IOL = +2mA
-5
5 -5
5 µA
2.4
- 2.4
-V
- 0.4
- 0.4 V
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
Document:1G5-0179
Rev.1
Page 7
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