VG4616321B View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG4616321B' PDF : 82 Pages View PDF
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note(1), (2))
Command
State CKEn-1 CKEn DQM(7) BS A9 A0-8 CS RAS CAS WE DSF
BankActivate & Masked Write Disable Idle(3)
H
X
X
V VVL L HHL
BankActivate & Masked Write Enable
Idle(3)
H
X
X
V VVL L HHH
BankPrecharge
Any
H
X
X
V LXL LHLL
PrechargeAll
Any
H
X
X
X HXL L H L L
Write
Active(3)
H
X
X
V LVLHL LL
Block Write Command
Active(3)
H
X
X
V LVLHL LH
Write and AutoPrecharge
Active(3)
H
X
X
V HVL H L L L
Block Write and AutoPrecharge
Active(3)
H
X
X
V HVL H L L H
Read
Active(3)
H
X
X
V LVLHLHL
Read and AutoPrecharge
Active(3)
H
X
X
V HVL H L HL
Mode Register Set
Idle
H
X
X
V LVL L L LL
Special Mode Register Set
Idle(5)
H
X
X
X XVL L L LH
No-Operation
Any
H
X
X
X XXL HHHX
Burst Stop
Active(4)
H
X
X
X XXL HHL L
Device Deselect
Any
H
X
X
X XXH X XXX
AutoRefresh
Idle
H
H
X
X XXL L LHL
SelfRefresh Entry
Idle
H
L
X
X XXL L LHL
SelfRefresh Exit
Idle
L
(SelfRefresh)
H
X
X XXH X XXX
L HHHX
Clock Suspend Mode Entry
Active
H
L
X
X XXX XXXX
Power Down Mode Entry
Any(6)
H
L
X
X XXH X XXX
L HHHL
Clock Suspend Mode Exit
Active
L
H
X
X XXX XXXX
Power Down Mode Exit
Any
L
H
X
X XXH X XXX
(Power-
Down)
L HHHL
Data Write/Output Enable
Active
H
X
L
X XXX XXXX
Data Write/Output Disable
Active
H
X
H
X XXX XXXX
Note: 1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Document:1G5-0145
Rev.1
Page 6
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