VM6101 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'VM6101' PDF : 17 Pages View PDF
VM6101
Figure 4. PWM duty cycle versus illumination
1.2
1.2
1.0
1.0
0.8 PWM_SENS = 9
0.8 PWM_SENS = 9
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.12E+00
10E+00
1E+00
10E+00
100E+00
1E+03
100EIl+lu0m0 inance1(Elx+)03
Illumination (lx)
Functional description
PWM_SENS = 18
PWM_SENS = 18
10E+03
10E+03
100E+03
100E+03
2.4
2.4.1
Two-wire serial interface
The VM6101 two-wire serial interface supports the following features:
● Standard-mode (100 kHz) I²C slave controller supporting 8-bit addressing
(7-bit address = 0x10 or 0010 000). SMBus compliant.
● Data and clock deglitching filters (double sampling)
● 8-bit index, i.e. 256 on-chip register address space
● Multiple read or write with index auto-increment
● Alternate address (0x11) selectable
Message types
The VM6101 registers are accessed by serial bus byte-oriented transactions. The following
message types are supported:
● Master write:
<S> <addr><w><A> <index><A> <data><A>[<data><A>...<data><A>]<P>
● Master read:
<S> <addr><r><A> [<data><A>...<data><A>]<data><nA><P>
● Combined format:
<S> <addr><w><A> <index><A>
<Sr> <addr><r><A> [<data><A>...<data><A>]<data><nA><P>
where:
S = start, Sr = repeated start, P = stop, A= acknowledge, nA = negative acknowledge
addr = 7-bit slave address, w = write bit (0), r = read bit (1),
index = 8-bit register address,
data = 8-bit register data, [] = optional.
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