VT5376 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'VT5376' PDF : 24 Pages View PDF
General features
VT5376
Figure 11. Frame dump mode timing diagram
400 x I2C single reads of pixel data
Set by user Set by 376
Set by 376
frame_dump_en
Reset by user
frame_dump_ready
frame_dump_pixel
frame_dump_completed
0
1
2
3
pixel address
398 399
NORMAL MODE
FRAME DUMP MODE
NORMAL MODE
7.7
Image streaming
To enter this test mode, set bit 4 of registry 0x62 to 1 (PCI_test_enable).
In this mode, the pins VGATE_ON, RESET_OUT, LASER_NEN and MOTION are used to
output serially fast video data in the form of 2 bits nibble + FST and QCLK.
On receipt of an FST (LASER_NEN) rising edge, NIB_EVEN (VGATE_ON) and NIB_ODD
(RESET_OUT) output data every 48 MHz clock cycle. The signals should be sampled 10 ns
after the FST rising edge, and then every 20.8 ns exactly, during 400 x 4 = 1600 cycles.
Groups of four consecutive NIB_EVEN and NIB_ODD must then be repackaged together to
form a single 8-bit pixel data. This format enables the pixels to be output at the same frame
rate as normal operation, and keeps I2C available to access the usual register settings.
For more details on image streaming please refer to the VT5376 Image System User
Manual.
Figure 12. Image streaming timing diagram
Motion (48 MHz QCLK)
Laser_NEN (FST)
VGate_On (NIB_EVEN) 6 4 2 0
Reset_Out (NIB_ODD) 7 5 3 1
reconstructed pixel data pixel_0[7:0] pixel_1[7:0]
22/31
Doc ID 13939 Rev 4
pixel_399[7:0]
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