VT5376 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
VT5376
STMicroelectronics
'VT5376' PDF : 31 Pages View PDF
VT5376
I2C control register map
Table 9. I2C control register map (continued)
Index
address
Bits
Name
R/W
Default
Description
0x4F [7:0] Exp max value
RO
0x61 [7:0] IMAGE[7:0]
RO
[0] Frame dump mode enable
RW
[1] Frame dump start
This registers holds the maximum
pixel value (before CDS) for the
current frame. It shows if some pixels
are saturated or not.
This register contains the pixel value
when the frame dump feature has
been activated (reg 0x62, bit 0).
To read the 400 pixels from the
captured frame, the register must be
read 400 consecutive times.
If set to 1, the device will capture a
single frame. When the frame is
0h
captured and ready to be downloaded
using reg 0x61, bit 2 (frame ready) is
set.
0h
Bit is set at start of frame dump
0x62
[2] Frame ready for download
RO
This bit is asserted when the captured
frame is ready to be downloaded using
0h
reg 0x61.
When frame download is complete,
bit 3 is reset.
[3] Frame upload complete
[4] PCI Test enable
0x82
[1] Timer ITR enable
0h
This flag is set when all 400 pixels
have been read by I2C host.
If set Motion, Laser_NEN, Reset_Out
R/W
0h
and VGate_On become PCI data
ouptuts (QCLK, FST and 2 bits serial
data).
R/W
1h
Timer interrupt enable.
1. Internal ACCUMULATOR is reduced from this value every time it is read.
2. Default changes to 1 for a laser system after host_config_done (that is, system set up for optics without a lens).
Doc ID 13939 Rev 4
17/31
Share Link: 