Colour Processor Interface ASIC
The diagram below, Figure X.Y, shows the activity that occurs on parallel port control and status lines during
the return of status information to the host via a Reverse ECP Mode transfer. NOTE - The actual data is
carried on the 8 data lines, which are not shown on the diagram.
Figure 2.11 : Typical Reverse ECP Status Transfer to Host
50 µs Div
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