VV5430 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'VV5430' PDF : 33 Pages View PDF
Write to Camera
VV5430
Setup Code_2
Header Code = 0010
Valid data bits: 12
The code_2 setup register is used to select read data, valid pixels and video output operating modes:
Bit
Function
Default
Comment
0
Primary read mode (A) enable
0
1
Secondary read mode (B) enable
0
Select Primary read mode A or B.
Note: bits 0,1 are mutually exclusive.
2
Pixel sample clock select (SEL0)
3
Pixel sample clock select (SEL1)
CPE
0
Pixel sample clock mode (PV/PVB). See
below.
4
Not used
0
MUST be set to 0
5
Enable free running pixel clock
0
Overrides SEL0 & SEL1.
6
Enable external pixel thresholds
0
Use external algorithm thresholds in expo-
sure controller
7
Not used
0
MUST be set to 0
8
Not used
0
MUST be set to 0
9
OE[0]
10
OE[1]
11
OE[2]
0
0
AVO output enable control bits [0..2]. See
Shuffle Modes above for explanation.
0
Table 16 : Setup Code_2
The table below shows the function of SEL0 and SEL1 (Bit 2 and Bit 3); the default value of SEL0 is set by the CPE pin level:
Bit 3
Bit 2
Pixel Clock (PV/PVB pins) function
0
0
Disable pixel clock output
0
1
Qualify full image area (as defined for CCIR or EIA)
1
0
Qualify central 256 x 256 pixels (CCIR only)
1
1
PV/PVB active only during interline periods of visible image lines.
Note. This mode is required for digitisation of standard video output.
Table 17 : SEL0 and SEL1 bits
Coarse and Fine Exposure Values.
Header Code (coarse)
Valid data bits: 9
= 0011
CD5430F-A
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