VV6301 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV6301' PDF : 51 Pages View PDF
CMOS Sensor; Customer Datasheet, Rev 3.0, 25 September 2000
VV5301 & VV6301
8. Serial Control Bus
8.1 General Description
Writing configuration information to the video sensor and reading both sensor status and configuration information back from the
sensor is performed via the 2-wire serial interface.
Communication using the serial bus centres around a number of registers internal to the video sensor. These registers store
sensor status, set-up, exposure and system information. Most of the registers are read/write allowing the receiving equipment to
change their contents. Others (such as the chip id) are read only.
The main features of the serial interface include:
• Broad-cast address to ease setting up multiple camera configurations.
• Variable length read/write messages.
• Indexed addressing of information source or destination within the sensor.
• Automatic update of the index after a read or write message.
• Message abort with negative acknowledge from the master.
• Byte oriented messages.
The contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line.
8.2 Serial Communication Protocol
The co- processor or host must perform the role of a communications master and the camera acts as either a slave receiver or
transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock video processor
frequency of up to 100 kHz. Since the serial clock is generated by the bus master it determines the data transfer rate. Data
transfer protocol on the bus is illustrated in Figure 12.
Start condition
Acknowledge
SDA
MSB
LSB
SCL
S
12 34 5 6 7
Address or data byte
8
A
P
Stop condition
Figure 12 : Serial Interface Data Transfer Protocol
8.3 Data Format
Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal data is produced by sampling
sda at a rising edge of scl. The external data must be stable during the high period of scl. The exceptions to this are start (S) or
stop (P) conditions when sda falls or rises respectively, while scl is high.
A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (Sr) followed
by another message.
The first byte contains the device address byte which includes the data direction read, (r), ~write, (~w), bit. The lsb of the address
byte indicates the direction of the message. If the lsb is set high then the master will read data from the slave and if the lsb is reset
low then the master will write data to the slave. After the r, ~w bit is sampled, the data direction cannot be changed, until the next
address byte with a new r, ~w bit is received.
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