VV6801C001 View Datasheet(PDF) - Vision
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MFG CO.
'VV6801C001' PDF : 23 Pages View PDF
VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
6.5.6 CR[8] - Output Channel Sample & Hold Enable
The sample and hold circuits in the AVO and AVORef output stages isolate the capacitive back injection
which occurs when an output channel is multiplexed onto the AC Coupling capacitor, which changes the
nature of the back injection:
Without sample and hold (CR[8] = 0 (default)), the interaction of the back injection and the column output
results in the AVO overshooting slightly before settling to the desired value
With sample and hold enabled (CR[8] = 1) the overshoot is eliminated, but the current pixel value will contain
a very small contribution from the previous pixel value read out on AVO
Note: CR[16] allows the output channel sample /hold capacitor to be isolated from the signal path.
6.5.7 CR[9] - Common Up the Black Reference Channels
There are two options for operating the four black reference output channels:
1. CR[9]=0 : Operate with the AVORef cycling between each of the four black output channels. AVORef
y will follow the shape of AVO as the AC coupling capacitor is cycling in the same way within both output
r stages. Any mismatch between the black reference output channels will appear as a four-cycle pattern
on AVORef.
a 2. CR[9]=1 : Parallel up the operation of the black output channels. AVORef represents the average of the
four black output channels.
in 6.5.8 CR[10] - Output Channel Clamp Enable
Setting CR[10] = 1 (default) clamps the four output channels that are multiplexed onto AVO to prevent them
going beyond the designed operating voltage range. This ensures that each output channel always has
enough time to recover from being inactive before outputing pixel data.
lim 6.5.9 CR[15:11] - 5-Bit Resistive DAC Data Value (D[5:0])
Data for the internal 5-bit Resistive Ladder DAC (default = 16). CR[15] is the MSB. See Section 2.8.
e 6.5.10CR[16] - Switch in Output Stage Sample/Hold Capacitors
r Setting CR[16] high isolates the output channel sample/hold capacitors from the signal path. By isolating
P these capacitors the output channels settle to the desired value in a shorter time.
Note: CR[16] should only be set high when the output channel sample/holds are disabled.
The primary use of this function is in Cine mode. In this mode only two of the four output channels are in use.
As the two output channels have only half the time to settle, compared with the normal readout sequence,
CR[16] should be set high to improve settling of the output channels.
6.5.11CR[18:17] - Vertical Cine Modes
3 hardwired subsampling modes are available. This simplifies the timing requirements for vertical
CR[18:17]
Vertical
Subsampling
Effect
00
None
None
01
1/2
Skip every 2nd line pair
10
1/4
Skip 3 line pairs in every 4
11
1/8
Skip 7 line pairs in every 8
Table 6.1 : Vertical Cine Mode
subsampling by removing the requirement to skip lines through timing generation. See also Section 5.4
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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
7. Detailed Operational Timing
The following Section describes in detail the recommended timing for the primary operating modes. There
are many possible timing schemes, with more flexible setup and holds, but the recommended timings are
safe. Specifically, timing diagrams and tables are given for:
• Normal Array Read
• Correlated Double Sampling (line by line)
Note: The timings in Section 7.1 to Section 7.5 have been expressed for a 5MHz PCK. The symbols
[T],[R],[F],[H],[L] signify Transitional edge, Rising edge, Falling edge, High Level and Low Level respectively.
7.1 System Clocks
Line and pixel timing is done in PCK’s, and all signals should change on the falling edge of PCK.
ry PCK Period
PCK Duty Cycle
ina Line Period
Min
100
40
1252 (for full
line readout)
Typ
200
-
1252
Max
Units
-
nS
60
%
-
PCK’s
Line Period (HCINE Mode)
740 (for full
740
-
subsampled
line readout)
lim Table 7.1 : System Clocks.
PCK’s
7.2 Line Start to PCK Timing
The relative timing of the Line Start pulse, LS, and the Pixel Clock, PCK, is extremely important for correct
e sensor operation. LS must be set up at least 20ns after the rising edge of PCK, no later than (PCK Period)/
Pr 4 after the rising edge of PCK, and must be held for four PCK cycles. This is illustrated below:
PCK
LS
min: 20ns
max: (PCK Period)/4
PCK [R]
changes pixel
on AVO
Figure 7.1 : Line Start to PCK Timing
7.3 Initial Power Up Timing
On powering up the array should be reset by VCLRB and HCLRB, to help the settling of the internal
references. An internal power-on-reset circuit generates RSTB, which can be used to reset the sensor.
The references VRT and Vbg must be stable before the first frame; this will be a function of the decoupling.
The internal reference and AC coupling stages should be put into sample mode by making SELRef, SAMRef,
and CLAMP high.
To ensure that the array is inactive until the first frame on power up FI, FR, LS, PCK, LCK and EVEN should
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