WE2408 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'WE2408' PDF : 36 Pages View PDF
WiNEDGE & WiRELESS
Winceiver WE2408
2.4GHz Single Chip FM Transceiver
If non-volatile memory is not available, correct can be done by checking and remember, in the RAM,
the RSSI value with no Rx signal, such as when LNA is off; or when antenna switch is off at Rx side;
or when Rx frequency is set to an impossible frequency.
If hardware method is preferred, the tolerance can be corrected by adjusting a trimmer pot meter.
RSSI SETTLING TIME
For 130kHz Rx bandwidth, ~25kHz FM deviation, and with recommended 10nF external capacitor
attached to RSSI pin, the RSSI reaches 80% of its final value in approximately 0.5ms.
If the FM signal carried is varying significantly in amplitude (e.g. FSK, switching between FM deviation
limits) then a longer integration time (i.e. larger RSSI capacitor) will be required for accurate
measurement of RX signal strength. Hence, settling time will be longer.
Also, for a narrower Rx bandwidth, the capacitor should be increased to integrate the received power
over a longer time. The increase should be inverse proportional to the bandwidth. RSSI response time
will also increase accordingly.
RX/TX RESPONSE TIME
RX/TX PLL LOCK TIME
The values shown below are based upon calculations using the component values shown in
application circuit with Rx and Tx charge pump currents being 1.0mA and 0.2mA respectively; and
reference frequency being 100kHz.
' Frequency
From start up
10MHz frequency change
1.0MHz frequency change
0.1MHz frequency change
Rx
8.5 ms
6.5 ms
5.0 ms
3.5 ms
Tx
17 ms
14 ms
11 ms
7 ms
Note: The settling time for Tx are based upon a 150 Hz high pass filter (HPF) cut off frequency. This
filter can be adjusted via the external Tx PLL loop filter components, or by the on-chip Tx charge
pump current selection. Settling time will be approximately inversely proportional to the required HPF
for the audio/data signal.
PLL Loop Filter
Faster PLL lock times are required in applications where time division duplexing or frequency hopping
techniques is used. On the contrary, narrow band audio applications, which need low VCO phase
noise, require tightening of PLL loop filter bandwidth. In the result, increases PLL lock time.
The loop filters employed are second order passive loop filters. Separate literatures are available for
various filter response considerations and calculation of filter components. Dumping factor, phase
noise and reference spurs are the main considerations beside lock time.
The following information are provided for PLL loop filter design:
Kvco
At different PLL voltage or different operating frequency, the VCO gain will be different. The accurate
Kvco value can be determined by measurement (VCO frequency change/PLL voltage change for 1
reference frequency step change).
© 2003 WiNEDGE & WiRELESS PTE LTD
Rev Date: 2003 May 23
Page 18
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