WED2ZLRSP01S35BC View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
MFG CO.
WED2ZLRSP01S35BC
White Electronic Designs Corporation
'WED2ZLRSP01S35BC' PDF : 13 Pages View PDF
White Electronic Designs
WED2ZLRSP01S
AC CHARACTERISTICS
Parameter
Symbol
166MHz
Min Max
150MHz
Min Max
133MHz
Min Max
100MHz
Min Max
Units
Clock Time
tCYC
6.0
6.7
7.5
10.0
ns
Clock Access Time
tCD
— 3.5 — 3.8 — 4.2 — 5.0
ns
Output enable to Data Valid
tOE
— 3.5 — 3.8 — 4.2 — 5.0
ns
Clock High to Output Low-Z
tLZC
1.5 — 1.5 — 1.5 — 1.5 —
ns
Output Hold from Clock High
tOH
1.5 — 1.5 — 1.5 — 1.5 —
ns
Output Enable Low to output Low-Z
tLZOE
0.0
—
0.0 — 0.0 — 0.0 —
ns
Output Enable High to Output High-Z
tHZOE
— 3.0 — 3.0 — 3.5 — 3.5
ns
Clock High to Output High-Z
tHZC
— 3.0 — 3.0 — 3.5 — 3.5
ns
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
tCH
2.2 — 2.5 — 3.0 — 3.0 —
ns
tCL
2.2 — 2.5 — 3.0 — 3.0 —
ns
tAS
1.5 — 1.5 — 1.5 — 1.5 —
ns
CKE# Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
tCES
1.5 — 1.5 — 1.5 — 1.5 —
ns
tDS
1.5 — 1.5 — 1.5 — 1.5 —
ns
tWS
1.5 — 1.5 — 1.5 — 1.5 —
ns
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
tADVS
1.5
1.5
1.5
1.5
ns
tCSS
1.5
1.5
1.5
1.5
ns
tAH
0.5 — 0.5 — 0.5 — 0.5 —
ns
CKE# Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
tCEH
0.5 — 0.5 — 0.5 — 0.5 —
ns
tDH
0.5 — 0.5 — 0.5 — 0.5 —
ns
tWH
0.5 — 0.5 — 0.5 — 0.5 —
ns
tADVH
0.5
—
0.5 — 0.5 — 0.5 —
ns
tCSH
0.5 — 0.5 — 0.5 — 0.5 —
ns
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is
sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low.
Both cases must meet setup and hold times.
4. Applies to each of the independent arrays.
AC TEST CONDITIONS
(0 ≤ TA ≤ 70°C, VCC = 2.5V ± 5%, Unless Otherwise Specified)
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
Value
0 to 2.5V
1.0V/ns
1.25V
See Output Load (A)
OUTPUT LOAD (A)
Dout
Zo=50Ω
RL=50Ω
30pF*
VL=1.25V
OUTPUT LOAD (B)
(for tLZC, tLZOE, tHZOE, and tHZC)
+2.5V
Dout
1667Ω
1538Ω
5pF*
*Including Scope and Jig Capacitance
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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