WM8731CSEFL/R View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

WM8731CSEFL/R

Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

Cirrus Logic 

Prev 21 22 23 24 25 26 27 28 29 30 Next

WM8731 / WM8731L

Production Data

The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high

frequency noise.

The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will

possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with

AVDD.

The device employs a pair of ADCs. The input can be selected from either the Line Inputs or the

Microphone input under software control. The two channels cannot be selected independently. The

control is shown in Table 5.

REGISTER

ADDRESS

BIT LABEL

0000100

2

Analogue

Audio Path

Control

INSEL

Table 5 ADC Software Control

DEFAULT

0

DESCRIPTION

Microphone/Line Input Select to ADC

1 = Microphone Input Select to ADC

0 = Line Input Select to ADC

The digital data from the ADC is fed for signal processing to the ADC Filters.

ADC FILTERS

The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data

from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 16

illustrates the digital filter path.

FROM ADC

DIGITAL

DECIMATOR

DIGITAL

DECIMATION

FILTER

DIGITAL

HPF

TO DIGITAL

AUDIO

INTERFACE

HPFEN

Figure 16 ADC Digital Filter

The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass

filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc

offset is continuously calculated and subtracted from the input signal. By setting HPOR the last

calculated dc offset value is stored when the high-pass filter is disabled and will continue to be

subtracted from the input signal. If the dc offset changes, the stored and subtracted value will not

change unless the high-pass filter is enabled. The software control is shown in Table 6.

REGISTER

BIT

ADDRESS

LABEL

0000101

0

ADCHPD

Digital Audio

Path Control

4

HPOR

Table 6 ADC Software Control

DEFAULT

DESCRIPTION

0

ADC High Pass Filter Enable

(Digital)

1 = Disable High Pass Filter

0 = Enable High Pass Filter

0

Store dc offset when High Pass

Filter disabled

1 = store offset

0 = clear offset

w

PD, Rev 4.9, October 2012

26

Share Link: