WM8731CSEFL/R View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
WM8731CSEFL/R
Cirrus Logic
'WM8731CSEFL/R' PDF : 65 Pages View PDF
WM8731 / WM8731L
USB MODE SAMPLE RATES
In USB mode the MCLK/crystal oscillator input is 12MHz only.
SAMPLING
RATE
ADC DAC
kHz
kHz
48
48
MCLK
FREQUENCY
MHz
12.000
BOSR
0
SAMPLE
RATE
REGISTER SETTINGS
SR3
SR2
SR1
0
0
0
Production Data
DIGITAL
FILTER
TYPE
SR0
0
0
44.1
44.1
12.000
1
1
0
0
0
1
(Note 2) (Note 2)
48
8
12.000
0
0
0
0
1
0
44.1
8
12.000
1
1
0
0
1
1
(Note 2) (Note 1)
8
48
12.000
0
0
0
1
0
0
8
44.1
12.000
1
1
0
1
0
1
((Note 1) (Note 2)
8
8
12.000
0
0
0
1
1
0
8
8
12.000
1
1
0
1
1
1
(Note 1) (Note 1)
32
32
12.000
0
0
1
1
0
0
96
96
12.000
0
0
1
1
1
3
88.2
88.2
12.000
1
1
1
1
1
2
(Note 3) (Note 3)
Table 21 USB Mode Sample Rate Look-up Table
Notes:
1. 8k not exact, actual = 8.021kHz
2. 44.1k not exact, actual = 44.118kHz
3. 88.2k not exact, actual = 88.235kHz
4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The table above can be used to set up the device to work with various sample rate combinations. For
example if the user wishes to use the WM8731/L in USB mode with the ADC and DAC sample rates
at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0,
SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0,
refer to Digital Filter Characteristics section for an explanation of the different filter types.
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital
signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB
mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over-
sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate
produced by the ADC and required by the DAC.
Example scenarios are, :-
1. with a requirement that the ADC data sampling rate is 8kHz and DAC data sampling rate is
48kHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 =
0.The ADC will then be exactly 8kHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects
data at exactly 48kHz ( derived from 12MHz/250 ).
2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz the device is
programmed with BOSR = 1 (272fs), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not
output data at exactly 8kHz, instead it will be 8.021kHz ( derived from 12MHz/272 x 2/11 ) and
the DAC at 44.118kHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore
results in the 8kHz and 44.1kHz audio data and (more importantly) the user must ensure that
the data across the digital interface is correctly synchronised at the 8.021kHz and 44.117kHz
rates.
w
PD, Rev 4.9, October 2012
44
Share Link: 