WM8766 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8766' PDF : 36 Pages View PDF
Production Data
DACPD [2:0]
000
001
010
011
100
101
110
111
DAC CHANNEL 1
Active
DISABLE
Active
DISABLE
Active
DISABLE
Active
DISABLE
Table 15 DAC Disable Control
DAC CHANNEL 2
Active
Active
DISABLE
DISABLE
Active
Active
DISABLE
DISABLE
WM8766
DAC CHANNEL 3
Active
Active
Active
Active
DISABLE
DISABLE
DISABLE
DISABLE
MASTER POWERDOWN
This control bit powers down the references for the whole chip. Therefore for complete powerdown,
all DACs should be powered down first before setting this bit.
REGISTER ADDRESS
0001010
Interface Control
BIT LABEL DEFAULT
4 PWRDNALL
0
DESCRIPTION
Master Power Down Bit:
0: Not powered down
1: Powered down
MASTER MODE SELECT
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK
and BCLK are outputs and are generated by the WM8766. In Slave mode LRCLK and BCLK are
inputs to WM8766.
REGISTER ADDRESS BIT
0001010
5
Interface Control
LABEL
MS
DEFAULT
0
DESCRIPTION
DAC Audio Interface Master/Slave
Mode Select:
0: Slave mode
1: Master mode
MASTER MODE LRCLK FREQUENCY SELECT
In Master mode the WM8766 generates LRCLK and BCLK. These clocks are derived from the
master clock and the ratio of MCLK to LRCLK is set by RATE.
REGISTER ADDRESS
0001010
Interface Control
BIT LABEL DEFAULT
8:6 RATE [2:0]
010
DESCRIPTION
Master Mode
MCLK:LRCLK Ratio Select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
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PD Rev 4.1 July 2005
27
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