WM8766 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8766' PDF : 36 Pages View PDF
Production Data
WM8766
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as crosstalk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
MASTER CLOCK TIMING
MCLK
t MCLKL
tMCLKH
t MCLKY
Figure 1 DAC Master Clock Timing Requirements
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK System clock pulse width
high
tMCLKH
MCLK System clock pulse width
low
tMCLKL
MCLK System clock cycle time
tMCLKY
MCLK Duty cycle
Power-saving mode activated
Normal mode resumed
Table 1 Master Clock Timing Requirements
TEST CONDITIONS
After MCLK stopped
After MCLK re-started
MIN
11
11
28
40:60
2
0.5
TYP
MAX
UNIT
1000
60:40
10
1
ns
ns
ns
Us
MCLK
cycle
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be
accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically
powered up, but a write to the volume update register bit is required to restore the correct volume settings.
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PD Rev 4.1 July 2005
7
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