WM8768GEDS/RV View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768GEDS/RV' PDF : 38 Pages View PDF
WM8768
Production Data
Note:
When MCLK is removed, digital volume settings are re-set to default (0dB). When MCLK is re-applied, the user
must write the desired volume level to the volume control registers.
L/RDAX[7:0]
ATTENUATION LEVEL
00(hex)
01(hex)
:
:
-∞ dB (mute)
-127.5dB
:
:
:
FE(hex)
FF(hex)
:
-0.5dB
0dB
Table 16 Digital Volume Control Attenuation Levels
SOFTWARE REGISTER RESET
Writing to register 11111 will cause a register reset, resetting all register bits to their default values.
This reset will last either 2*MCLK periods or until another write is made to the serial interface.
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8768 can be configured using the Control Interface. All unused bits should be set to ‘0’.
REGISTER B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
R0(00h)
0 0 0 0 0 0 0 UPDATE
R1(01h)
0 0 0 0 0 0 1 UPDATE
B4
B3
B2
B1
LDA1[7:0]
RDA1[7:0]
B0
DEFAULT
011111111
011111111
R2(02h)
000 0010
PL[8:5]
PDWN DEEMP MUTE
IZD
ATC
100100000
All DAC ALL DAC All DAC
R3(03h)
R4(04h)
R5(05h)
R6(06h)
R7(07h)
R8(08h)
R9(09h)
R10(0Ah)
R12(0Ch)
R13(0Dh)
R14(0Eh)
R15(0Fh)
R31(1Fh)
000 0011
PHASE[8:6]
DACIWL[5:4]
DACBCP DACLRP DACFMT[1:0] 000000000
0 0 0 0 1 0 0 UPDATE
LDA2[7:0]
011111111
0 0 0 0 1 0 1 UPDATE
RDA2[7:0]
011111111
0 0 0 0 1 1 0 UPDATE
LDA3[7:0]
011111111
0 0 0 0 1 1 1 UPDATE
RDA3[7:0]
011111111
0 0 0 1 0 0 0 UPDATE
MASTDA[7:0]
011111111
000 1001
DEEMP[8:6]
DMUTE[5:3]
DZFM[2:1]
ZCD 000000000
000 1010
DACRATE[8:6]
DACMS PWRDN
ALL
DACD[3:1]
0
010000000
000 1100
0
0
MPD
0
0
0
0
0
0
000000000
0 0 0 1 1 0 1 UPDATE
0 0 0 1 1 1 0 UPDATE
000 1111
0
0
001 1111
LDA4[7:0]
011111111
RDA4[7:0]
011111111
0
MPD DEEMP PHASE4 DMUTE DZFM4 DACD4 000000000
4
4
RESET
000000000
w
PD Rev 4.3 July 2010
32
Share Link: 
