WM8772 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772' PDF : 73 Pages View PDF
Production Data
WM8772EDS – 28 LEAD SSOP
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS BIT
0000010
3
DAC Channel Control
LABEL
ATC
DEFAULT
0
DESCRIPTION
Attenuator Control Mode:
0: Right channels use right
attenuations
1: Right channels use left
attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS BIT LABEL DEFAULT
DESCRIPTION
0000010
4
IZD
DAC Channel Control
0
Infinite Zero Mute Enable
0 : Disable inifinite zero mute
1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that
stereo channel outputs to be muted to VMID. Mute will be removed as soon as that stereo channel
receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS BIT
0000010
8:5
DAC Control
LABEL
PL[3:0]
DEFAULT
1001
PL[3:0]
0000
0001
DESCRIPTION
Left
Output
Right
Output
Mute
Mute
Left
Mute
0010
Right
Mute
0011
0100
(L+R)/2
Mute
Mute
Left
0101
Left
Left
0110
Right
Left
0111
(L+R)/2 Left
1000
Mute
Right
1001
1010
Left
Right
Right
Right
1011
(L+R)/2 Right
1100
Mute
(L+R)/2
1101
Left
(L+R)/2
1110
Right
(L+R)/2
1111
(L+R)/2 (L+R)/2
w
PD Rev 4.2 October 2005
31
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