WM8781GEDS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8781GEDS' PDF : 21 Pages View PDF
WM8781
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Production Data
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
Table 1 Master Clock Timing Requirements
SYMBOL
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
MIN
11
11
28
40:60
AUDIO INTERFACE TIMING – MASTER MODE
TYP
MAX
60:40
UNIT
ns
ns
ns
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DOUT propagation delay from BCLK falling edge
SYMBOL
tDL
tDDA
MIN
TYP
MAX
0
10
0
10
Table 2 Digital Audio Data Timing - Master Mode
UNIT
ns
ns
w
PD, January 2012, Rev 4.5
8
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