WM8804GEDS/R View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/R' PDF : 66 Pages View PDF
Production Data
WM8804
REGISTER
ADDRESS
R16
RXCHAN4
10h
(read-only)
BIT
LABEL
CHANNEL DEFAULT
STATUS
BIT
3:0
FREQ[3:0]
27:24
0001
5:4 CLKACU[1:0]
29:28
11
Table 43 S/PDIF Receiver Channel Status Register 4
DESCRIPTION
Indicated Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3)
for full details.
Clock Accuracy of Received Clock
00 = Level II
01 = Level I
10 = Level III
11 = Interface frame rate not matched to
sampling frequency.
REGISTER BIT
ADDRESS
R17
0
RXCHAN5
11h
(read-only)
3:1
LABEL
MAXWL
RXWL[2:0]
CHANNEL
STATUS
BIT
32
35:33
DEFAULT
DESCRIPTION
1
Maximum Audio Sample Word Length
0 = 20 bits
1 = 24 bits
Note: see table in description of bits 3:1 of
this register,
000
Audio Sample Word Length
000: Word length not indicated
RXWL[2:0] MAXWL==1 MAXWL==0
001
20 bits
16 bits
010
22 bits
18 bits
100
23 bits
19 bits
101
24 bits
20 bits
110
21 bits
17 bits
7:4 ORGSAMP
[3:0]
39:36
0000
All other combinations are reserved and
should not be used. See note 1.
Original Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3)
for full details.
Table 44 S/PDIF Receiver Channel Status Register 5
Note 1:
MAXWL and RXWL[2:0] bits in recovered channel status data are used to truncate digital audio
interface transmitted data. Truncation replaces the lower data bits with 0. Truncation can be masked
using the WL_MASK control bit. Truncation can be masked by the WL_MASK Refer to received
channel status bit description.
w
PD Rev 4.1 September 2007
37
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