WM8804GEDS/R View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/R' PDF : 66 Pages View PDF
WM8804
REGISTER BIT
ADDRESS
R23
3:0
GPO0
17h
LABEL
GPO0[3:0]
R24
3:0
GPO1[3:0]
GPO1
18h
R26
7:4
GPO2[3:0]
GPO2
1Ah
DEFAULT
Production Data
DESCRIPTION
0000
Flags and Status bits available on GPO pins
0111
0100
0000 = INT_N
0001 = V
0010 = U
0011 = C
0100 = TRANS_ERR
0101 = SFRM_CLK
0110 = 192BLK
0111 = UNLOCK
1000 = NON_AUDIO
1001 = CSUD
1010 = DEEMPH
1011 = CPY_N
1100 = ZEROFLAG
1101 = 0
↓
1111 = 0
R27
AIFTX
1Bh
1:0 AIFTX_FMT[1:0]
3:2
AIFTX_WL[1:0]
4
AIFTX_BCP
5
AIFTX_LRP
R28
AIFRX
1Ch
1:0
AIFRX_FMT[1:0]
3:2
AIFRX_WL[1:0]
4
AIFRX_BCP
Note: GPO1 and GPO2 is only available in 2-
wire software control mode.
10
Audio Data Format Select
11: DSP mode
10: I2S mode
01: Left justified mode
00: Right justified mode
01
Audio Data Word Length Select
11: 24 bits
10: 24 bits
01: 20 bits
00: 16 bits
0
BCLK Invert (for master and slave modes)
0 = BCLK not inverted
1 = BCLK inverted
0
Right, left and I2S modes – LRCLK polarity and
DSP mode select
1 = invert LRCLK polarity / DSP Mode B
0 = normal LRCLK polarity / DSP Mode A
10
Audio Data Format Select
11: DSP mode
10: I2S mode
01: Left justified mode
00: Right justified mode
01
Audio Data Word Length Select
11: 24 bits
10: 24 bits
01: 20 bits
00: 16 bits
0
BCLK Invert (for master and slave modes)
0 = BCLK not inverted
1 = BCLK inverted
w
PD Rev 4.1 September 2007
60
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