WM8804GEDS/R View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/R' PDF : 66 Pages View PDF
WM8804
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
tBCH
tBCL
tBCY
LRCLK
DIN
DOUT
tDS
tDD
tLRH
tDH
tLRSU
Production Data
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
tBCY
tBCH
tBCL
tLRSU
LRCLK hold time from
tLRH
BCLK rising edge
DIN set-up time to BCLK
tDS
rising edge
DIN hold time from BCLK
tDH
rising edge
DOUT propagation delay
tDD
from BCLK falling edge
Table 3 Digital Audio Data Timing – Slave Mode
TEST CONDITIONS
MIN
TYP
MAX
50
20
20
10
10
10
10
0
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.1 September 2007
8
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