WM8804GEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/V' PDF : 66 Pages View PDF
Production Data
REGISTER BIT
ADDRESS
R20
3:0
SPDTX3
14h
5:4
7:6
R21
3:0
SPDTX4
15h
5:4
6
7
R22
0
SPDTX5
16h
3:1
7:4
w
LABEL
SRCNUM
[3:0]
CHNUM1[1:0]
CHNUM2[1:0]
FREQ[3:0]
CLKACU[1:0]
TXSRC
TXSTATSRC
MAXWL
TXWL[2:0]
ORGSAMP
[3:0]
DEFAULT
WM8804
DESCRIPTION
0000
00
00
0001
11
1
0
1
101
0000
Source Number
Refer to S/PDIF specification (IEC 60958-3) for
full details.
Channel Number for Subframe 1
CHNUM1
Channel Status Bits[21:20]
Function
00
Do not use channel number
01
Send to Left Channel
10
Send to Right Channel
11
Do not use channel number
Channel Number for Subframe 2
CHNUM2
Channel Status Bits[23:22]
Function
00
Do not use channel number
01
Send to Left Channel
10
Send to Right Channel
11
Do not use channel number
Indicated Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3) for
full details.
0001 = Sampling Frequency not indicated.
Clock Accuracy of Transmitted Clock
00 = Level II
01 = Level I
10 = Level III
11 = Interface frame rate not matched to
sampling frequency.
S/PDIF Transmitter Data Source
0 = S/PDIF Received Data – SPDIFTXCLK
Source = CLK2
1 = Digital Audio Interface Received Data –
SPDIFTXCLK Source = MCLK Input/Output
Signal at MCLK Pin
S/PDIF Transmitter Channel Status Data
Source
0 = Received channel status data
1 = Transmit channel status registers
Note : Only used if TXSRC=0
Maximum Audio Sample Word Length
0 = 20 bits
1 = 24 bits
Audio Sample Word Length
Used with MAXWL to indicate Tx word length
000 = Word length not indicated
TXWL[2:0] MAXWL==1 MAXWL==0
001
20 bits
16 bits
010
22 bits
18 bits
100
23 bits
19 bits
101
24 bits
20 bits
110
21 bits
17 bits
All other combinations reserved
Original Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3) for
full details.
PD, Rev 4.5, March 2009
59
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