WT21 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'WT21' PDF : 54 Pages View PDF
Figure 24: PCM Slave Timing Short Frame Sync
8.1.9 PCM_CLK and PCM_SYNC Generation
WT21 has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by Direct Digital Synthesis(DDS) from WT21 internal 4MHz clock. Using
this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is
generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a
greater range of frequencies to be generated with low jitter but consumes more power). This
second method is selected by setting bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32.
When in this mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16
cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
Equation XXX describes PCM_CLK frequency when being generated using the internal 48MHz
clock:
Equation 2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As
an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
8.1.10 PCM Configuration
The PCM configuration is set using the PS Keys, PSKEY_PCM_CONFIG32 described in Table 14,
PSKEY_PCM_LOW_JITTER_CONFIG in Table 13, and PSKEY_PCM_SYNC_MULT in Table 15. The
default for PSKEY_PCM_CONFIG32is 0x00800000, i.e., first slot following sync is active, 13-bit
linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from
4MHz internal clock with no tri-state of PCM_OUT.
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