11.3.2 Digital
Digital Terminals
Input Voltage Levels
VIL input logic level low 1.7V ≤ VDD ≤ 3.6V
VIH input logic level high 1.7V ≤ VDD ≤ 3.6V
Output voltage levels
VOL output logic level low 1.7V ≤ VDD ≤ 3.6V,
(Io = 4.0 mA)
VOH output logic level high 1.7V ≤ VDD ≤ 3.6V,
(Io = -4.0 mA)
Input Tri-state Current with:
Strong pull-up
Strong pull-down
Weak pull-up
Weak pull-down
I/O pad leakage curren
Cl input capacitance
Min
-0.4
0.7VDD
Typ
Max
Unit
-
0.25xVDD
V
-
VDD+0.3
V
-
-
VDD-0.4
-
0.125
V
VDD
V
-100
-40
-10
µA
10
40
100
µA
-5
-1
-0.2
µA
0.2
1
5
µA
-1
0
1
µA
1
-
5
pF
Table 25: Digital terminal electrical characteristics
11.3.3 Reset
Power-on Reset
VDD_CORE (a falling threshold
VDD_CORE (a rising threshold
Hysteresis
Min
Typ
Max
Unit
1.13
1.24
1.3
V
1.2
1.31
1.35
V
0.05
0.07
0.15
V
(a VDD_CORE is a core voltage supplied by the internal 1.5 V voltage regulator.
Table 26: Power on reset characteristics
11.3.4 32 kHz External Reference Clock
Parameter
Frequency
Frequency
deviation
Frequency
deviation
Input high level
Input low level
Duty cycle
Rise and fall
time
Integrated
frequency jitter
Conditions/Not
es
@25°C
-25°C to 85°C
Square wave
Square wave
Square wave
Integrated over
the band 200 Hz
to 15 kHz
Min
32748
-
Specifications
Nom
32768
-
Max
32788
20
-
-
150
0.625xVDD_PADS
-
-
-
-
0.425xVDD_PADS
30
-
70
-
-
50
-
-
-
Table 27: External Reference Clock
Units
Hz
+/- ppm
+/- ppm
V
V
%
ns
Hz (rms)
Bluegiga Technologies Oy
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