XE3005 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'XE3005' PDF : 37 Pages View PDF
XE3005/XE3006
- Disable time (t disable) between the last rising edge of SCK and the rising edge of SS.
- SCK frequency (FSCK)
Delay
t recover
t disable
F SCK
Min
125
2 x Tmaster
Max
-
-
0.5 x Fmaster
Unit
ns
ns
Hz
Comments
Tmaster = clock period of the master clock MCLK
Fmaster = frequency of the master clock MCLK
3.3.2 SPI Interface Modes
There are two SPI modes: read and write.
3.3.2.1 Read Mode
Read communication always takes place in pairs of bytes. A read request of 2 bytes is sent on the MOSI line. The
content of the addressed register, one byte, is dumped on the MISO line during the transmission of the second byte on
the MOSI. The formats of one byte are the following:
bit
7
6
5
4
3
2
1
0
mosi
1
1
0
msb
A (4:0)
lsb
bit
7
6
5
4
3
2
1
0
miso
msb
D(7:0)
lsb
ss
sck
mosi
1 1 0 A4 A3 A2 A1 A0 1 1 0
request (read <address A(4:0)>)
miso
msb
lsb
read data D(7:0) of address A(4:0)
Figure 17: SPI signal timing in read mode
3.3.2.2 Write Mode
Write communication always takes place in pairs of bytes. The format of the 2 bytes is:
Bit
7
6
mosi
1
0
Bit
7
6
mosi
msb
© Semtech 2005
5
4
3
0
msb
5
4
3
D(7:0)
16
2
1
A(4:0)
2
1
0
lsb
0
lsb
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