XR16C2852 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C2852' PDF : 51 Pages View PDF
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift Data Bit
Register (RSR)
Validation
xr
REV. 2.1.1
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock
128 bytes by 11-bit
wide FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive
Data FIFO
Receive
Data
Data Bit
Validation
Receive Data Characters
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data falls to 8 RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO Trigger=16 RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to 24 RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 10 (Table 10 on page 27).
14
Share Link: 
