XR16C2852CJ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C2852CJ' PDF : 51 Pages View PDF
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
xr
REV. 2.1.1
2.21 Internal Loopback
The 2852 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 13. INTERNAL LOOP BACK IN CHANNELS A AND B
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
CD#
OP1#
OP2#
TXA/TXB
RXA/RXB
RTSA#/RTSB#
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
20
Share Link: 
