XR16C2852IJTR-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C2852IJTR-F' PDF : 51 Pages View PDF
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
xr
REV. 2.1.1
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
TSI
ISR is read
TX FIFO fills up
to trigger level
TWRI
TX FIFO drops
below trigger level
Last Data Byte
Transmitted
S D0:D7 T
TSRT
TX FIFO
Empty
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Start
Bit
Stop
Bit
TX
(Unloading)
S D0:D7 T S D0:D7 T
IER[1]
enabled
ISR Read
D0:D7 S D0:D7 T
S D0:D7 T S D0:D7 T
TSRT
TSI
Last Data Byte
Transmitted
S D0:D7 T
ISR Read
INT*
TXRDY#
TX FIFO fills up
to trigger level
TWRI
TX FIFO
Full
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
TWT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
46
Share Link: 
