XR16C854CQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C854CQ' PDF : 54 Pages View PDF
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
TSI
ISR is read
TX FIFO fills up
to trigger level
TWRI
TX FIFO drops
below trigger level
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
Last Data Byte
Transmitted
S D0:D7 T
TSRT
TX FIFO
Empty
TXDMA#
48
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