XR16C864IQTR-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C864IQTR-F' PDF : 51 Pages View PDF
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.2.0
2.12 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the TX FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
2.12.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.12.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
T rans m it
H o ld in g
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X
Clock
Transmit Shift Register (TSR)
M
L
S
S
B
B
TXNOFIFO1
2.12.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the TX FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when
the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/TX FIFO becomes empty.
14
Share Link: 
