XR16C864IQTR-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C864IQTR-F' PDF : 51 Pages View PDF
REV. 2.2.0
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D
RX
INT
RXRDY#
Start
Bit
Stop
Bit
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
TSSI
RX FIFO drops
below RX
Trigger Level
RX FIFO fills up to RX
Trigger Level or RX Data
TSSR
Timeout
FIFO
Empties
IOR#
(Reading data out
of RX FIFO)
TRRI
TRR
RXFIFODMA
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
TSI
ISR is read
TX FIFO fills up
to trigger level
TWRI
TX FIFO drops
below trigger level
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
Last Data Byte
Transmitted
S D0:D7 T
TSRT
TX FIFO
Empty
TXDMA#
49
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