XR16V794 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16V794' PDF : 53 Pages View PDF
REV. 1.0.1
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FCTR BIT-2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
FCTR BIT-1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FCTR BIT-0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RTS/DTR HYSTERESIS
(CHARACTERS)
0
+/- 4
+/- 6
+/- 8
+/- 8
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
4.13 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bits 3:0 provide single or dual consecutive
character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
• Logic 0 = Automatic CTS/DSR flow control is disabled (default).
• Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts
(HIGH). Transmission resumes when CTS/DSR# pin is asserted (LOW). The selection for CTS# or DSR# is
through MCR bit-2.
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/
DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level
and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will re-
assert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-
7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection
for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when
hardware flow control is disabled.
• Logic 0 = Automatic RTS/DTR flow control is disabled (default).
• Logic 1 = Enable Automatic RTS/DTR flow control.
39
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