XR16V798 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16V798' PDF : 56 Pages View PDF
REV. 1.0.1
XR16V798
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X Clock
64 bytes by 11-bit
wide
FIFO
Receive Data
Byte and Errors
Receive Data Shift Data Bit
Register (RSR) Validation
Receive Data Characters
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
Receive
Data FIFO
Receive
Data
Data falls to 8
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
FIFO Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to 24
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 8 (see Table 14).
2.9 THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 are shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
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