XR21V1414 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR21V1414' PDF : 32 Pages View PDF
XR21V1414
4-CH FULL-SPEED USB UART
REV. 1.1.0
3.3.8 ERROR_STATUS Register Description - Read-only
This register reports any errors that may have occurred on the line such as break, framing, parity and overrun.
ERROR_STATUS[2:0]: Reserved
These bits are reserved. Any values read from these bits should be ignored.
ERROR_STATUS[3]: Break error
• Logic 0 = No break condition
• Logic 1 = A break condition has been detected (clears after read).
ERROR_STATUS[4]: Framing Error
• Logic 0 = No framing error
• Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected.
ERROR_STATUS[5]: Parity Error
• Logic 0 = No parity error
• Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
• Logic 0 = No overrun error
• Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received.
ERROR_STATUS[7]: Break Status
• Logic 0 = Break condition is no longer present.
• Logic 1 = Break condition is currently being detected.
3.3.9 TX_BREAK Register Description (Read/Write)
Writing a non-zero value to this register causes a break condition to be generated continuously until the
register is cleared. If data is being shifted out of the TX pin, the data will be completely shifted out before the
break condition is generated.
3.3.10 XCVR_EN_DELAY Register Description (Read/Write)
XCVR_EN_DELAY[3:0]: Turn-around delay
This is the number of bit times to wait before changing the direction of the transceiver from transmit to receive
when half-duplex mode is enabled.
XCVR_EN_DELAY[3:0]: Reserved
These bits are reserved and should be ’0’.
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