XR28V382IL32-0A-EB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR28V382IL32-0A-EB' PDF : 39 Pages View PDF
XR28V382
3.3V DUAL LPC UART WITH 128-BYTE FIFO
REV. 1.0.1
2.1.1 Global Control Registers
2.1.1.1 Software Reset Register
Software Reset resets the Device Configuration registers to their factory defaults. Strapping pins from Table 1
are not sampled during a software reset.
Bit [0]: Software reset
x Logic 0 = Disable software reset (default).
x Logic 1 = Enable software reset. After the software reset, this bit will turn to ’0’ automatically.
Bits [7:1]: Reserved
2.1.1.2 Logic Device Number Register - Read/Write
This register selects device configuration register set among the 2 channel UARTs and the watchdog timer.
Bits [7:0]: Select different device configuration register set.
x 0x00 = Select UART A device configuration register (default).
x 0x01 = Select UART B device configuration register.
x 0x08 = Select Watchdog Timer device configuration register.
2.1.1.3 Device ID MSB/LSB Register -Read only
DEV_ID_M (0x20): This register provides upper byte device ID for XR28V382. The default value is 0x03.
DEV_ID_L (0x21): This register provides lower byte device ID for XR28V382. The default value is 0x82.
2.1.1.4 Vendor ID MSB/LSB Register -Read only
VID_M (0x23): This register value provides upper byte of Exar’s Vendor ID. The default value is 0x13.
VID_L (0x24): This register value provides lower byte of Exar’s Vendor ID. The default value is 0xA8.
2.1.1.5 Clock Select Register - Read/Write
This register selects the clock frequency.
Bit [0]: Clock select
x Logic 0 = The CLKIN is 24 MHz (default).
x Logic 1 = The CLKIN is 48 MHz.
Bits [7:1]: Reserved
2.1.1.6 Watchdog Timer Control Register - Read/Write
This register controls the watchdog timer.
Bit [0]: Assert a low pulse from WDTOUT#/PS_WDT pin
x Logic 0 = Watchdog timer (WDT) will assert a low pulse from WDTOUT#/PS_WDT pin (default).
x Logic 1 = Watchdog timer (WDT) will not assert a low pulse from WDTOUT#/PS_WDT pin, but the timeout
status will be set.
Bit [1]: Restart timer
x Logic 0 = Read watchdog timer (WDT) will restart the timer (default).
x Logic 1 = Read watchdog timer (WDT) will not restart the timer.
Bits [7:2]: Reserved
20
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