XR68C192CJ View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XR68C192CJ

DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

Exar Corporation 

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XR68C92/192

A3 A2 A1 A0

0000

1000

0000

1000

0000

1000

0001

1001

0001

1001

0010

1000

0011

1011

0011

1011

0100

0100

0101

0101

0110

0111

1101

1101

1110

1110

1111

1111

Register

[Default]

MRA0 [00]

MRB0[00]

MRA1[00]

MRB1[00]

MRA2[00]

MRB2[00]

CSRA[00]

CSRB[00]

SRA[00]

SRB[00]

BIT-7

BIT-6

Watch

dog timer

RX

trigger

level

RX

RTS

control

RX

trigger

level

Channel

mode

select

Channel

mode

select

RX

clock

RX

clock

Received Framing

break

error

BIT-5

TX

trigger

level

Error

mode

TX

RTS

control

RX

clock

Parity

error

BIT-4

TX

trigger

level

Parity

mode

TX

CTS

control

RX

clock

Overrun

error

BIT-3

Not

used

Parity

mode

Stop

bit

length

TX

clock

TX

empty

CRA[00]

CRB[00]

Misc.

Misc.

Misc.

Misc.

TX

command command command command disable

RHRA[XX]

RHRB[XX]

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

THRA[XX]

THRB[XX]

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

ACR[00]

Baud

rate

set

select

C/T

mode

C/T

mode

C/T

mode

Delta

IP3

INT

IPCR[00]

Delta

IP3

Delta

IP2

Delta

IP1

Delta

IP0

IP3

input

ISR[00]

Input

port

change

Delta

break B

RXB

ready/

FIFO full

TXB

ready

C/T

ready

IMR[00]

Input

port

change

Delta

break B

RXB

ready/

FIFO full

TXB

ready

C/T

ready

CTU[00]

Bit-15

Bit-14

Bit-13

Bit-12

Bit-11

CTL[00]

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

IPR[XX]

Not

Not

IP5

IP4

IP3

Used

Used

OPCR[00]

OP7

OP6

OP5

OP4

OP3

STCC[XX]

X

X

X

X

X

SOPB[00]

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

SPCC[XX]

X

X

X

X

X

ROPB

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

BIT-2

BIT-1

Baud

rate

ext. 2

Parity

type

Not

used

Word

length

Stop

bit

length

TX

clock

TX

ready

TX

enable

Bit-2

Stop

bit

length

TX

clock

RX

FIFO

full

RX

disable

Bit-1

Bit-2

Bit-1

Delta

IP2

INT

Delta

IP1

INT

IP2

input

IP1

input

Delta

break A

RXA

ready/

FIFO full

Delta

break A

RXA

ready/

FIFO full

Bit-10

Bit-9

Bit-2

Bit-1

IP2

IP1

OP3

X

Bit-2

X

Bit-2

OP2

X

Bit-1

X

Bit-1

BIT-0

Baud

rate

ext. 1

Word

length

Stop

bit

length

TX

clock

RX

ready

RX

enable

Bit-0

Bit-0

Delta

IP0

INT

IP0

input

TXA

ready

TXA

rdy

Bit-8

Bit-0

IP0

OP2

X

Bit-0

X

Bit-0

Rev. P1.10

16

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