XR68C681
D.4 External Inputs
% + % + # , (% #,
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' '3 % ((- %'% + %(% $
'(% + ' % ,% % '
%'(+& ''3 %(-" ($ + %
! (%" (% 5 /5 ''3 %(-K ( ''3
%' -(%% % $($
$(%'%%( ( (% $ ( +'(" %
% Section E
D.5 Clock Select Registers, CSRA and CSRB
# Figure 5" '3 ' -(%% %
14 5.% ''3 %' -(%% %
% ' %' (' ''3 %(-% ( $(
%(% $ '(% + ' % %
% %' 1 $(++ %$$ ( %
+ *0" .( " %
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''3 %' $((- %(% $ '(%
Bit 7
Bit 6
Bit 5
'( '3 '
Table 9
Bit 4
Bit 3
Bit 2
Bit 1
%( '3 '
Bit 0
Table 8. Bit Format of the Clock Select Registers, CSRA and CSRB
Field
CSR[7:4]
CSR[3:0]
Bit Rate
ACR[7] = 0 (Bit Rate Set #1)
ACR[7] = 1 (Bit Rate Set #2)
X=0
X=1
X=0
X=1
6
@6
@6
6
1=6
1=6
1=6
1=6
6
6
1
1/
1
1/
/
==7
/
==7
<<7
<<7
6
6@/7
6@/7
=
67
=
67
=<
=<
=<
=<
@
<
<
@
/
/
/
/
1<=7
7
7
1<=7
(
(
(
(
2! /5
2! /5
2! /5
2! /5
2! 5
2! 5
2! 5
2! 5
Table 9. Bit Format of the Clock Select Registers CSR[3:0] and CSR[7:4]