XR68C681
I. PROGRAMMING
( + (% -$ & ((- '
$% ( ( -(%%" ( (
+$'3 (% ($$ & %% -(%% (' '
$ & , -(% $$%%(- (% % (
Table 1 $ % '% '% + "
#" #" ," $ , -(%% $ ((((G%
#; / (- (" ' % $ !'(%$ (+
'% + ' -(%% ' -$" %('
'( ' -% & % ( ( (
!" ' -(- + (% ' ' (
$ (% (- '($ & % ( '( +
% ' ' # -" ' -% -(%%
(' ' '( %( ( % $
$ & ( %( '( $(%$"
$ '( ' -% % $ $ &
. (% %$
$" '$" ''3 %'" $ %% -(%%
$('$ + ' ' ($ ($$
( Table 10 %(G% ( %%(-% +
' -(%
Bit 7
Rx RTS
Control
J 8
J E%
Bit 6
Bit 5
Rx Int Select Error Mode
J5E
J ::
J
J *'3
Bit 4
Bit 3
Parity Mode Select
J A( ,(&
J ' ,(&
J 8 ,(&
J ( $
Bit 2
Parity Select
J 2
J $$
Bit 1
Bit 0
Number of Bits/Char.
J 6
J /
J @
J <
Table 20. Mode Registers 1: MR1A, MR1B
Bit 7
Bit 6
Channel Mode
J 8
J 2'
J :' :
J :
Bit 5
Tx RTS
Control
J 8
J E%
Bit 4
CTS Enable
Tx
J 8
J E%
Bit 3
Bit 2
Bit 1
Stop Bit Length
Bit 0
J 6/1
J /6
J /<<
1 J @6
= J <1
6 J <@6
/ J 1<
@ J
< J 6/1
J /6
J /<<
* J @6
J <1
J <@6
2 J 1<
J
Table 21. Mode Register 2: MR2A, MR2B
Bit 7
Bit 6
Bit 5
'( '3 '
Table 6
Bit 4
Bit 3
Bit 2
Bit 1
%( '3 '
Table 6
Bit 0
Table 22. Clock Select Registers: CSRA, CSRB
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