XR68C681
Bit 7
Input Port
Change
J 8
J E%
Bit 6
Delta Break
B
J 8
J E%
Bit 5
RXRDY/
FFULLB
J 8
J E%
Bit 4
TXRDYB
J 8
J E%
Bit 3
Counter
Ready
J 8
J E%
Bit 2
Delta Break
A
J 8
J E%
Bit 1
RXRDY/
FFULLA
J 8
J E%
Table 5. Interrupt Status Register - (ISR) Bit Format
Bit 0
TXRDYA
J 8
J E%
(- ($ ' + % (% (% $+($
ISR[7]: Input Port Change of State:
#+ (% ( (% -(' HI" H' - + %I %
$'$ #, #,1 (% % $ %(' (%
( & $(- #, (+ #M@N J #M@N (%
'$ , % $ #, *& $(-
#," % ( $(4
($(($ # , ( ' -$ %
+( % + ($ ( %" +(-
- +
$($ $%'(( + #," % %
Section E
,% ( $ (% ( '$(("
% % $ (-%4
A( ( $ ( +
!((& -(%" M14N # (% %"
% (% %'(+&(- (' ( (% % $ (--
H# , -I ( C%
A( -(' HI #M@N
ISR[6] Delta Break Indicator - Channel B:
A (% ( (% %" ( ($('% ' * '(
% $'$ -((- $ + '($ 3
(% ( (% '$ % , (3%
' * H22 *27 9802 #82,I
'$ (+( ( .%
%% *27 '$((" % % Section G.2
ISR[5] RXRDYB/FFULLB - Channel B Receiver
Ready or FIFO Full
+'( + (% ( (% %'$ & -(-
*M/N #+ -$ % '( $&
($(' 5E*" ( ($('% %
' ' + $ (% ( 9* $ (% $& $ &
, (% ( (% % ' ' (% %+$
+ '($ % (+ -(% 9* $ (% '$
, $% 9* #+ %(
' '% ( 9* + $ (" ( (
% -( + 9* (% H$I
#+ (% ( (% -$ % # ($(' ::*"
( (% % ' ' (% %+$ +
9* $ %+ '%% 9* ' + (%
( (% '$ , $% 9*K $ &
H(-I # " 3(- + ! ' ' #+
' ' (% ((- ( '% 9* (% +"
(% ( ( % -( + $ ("
' ' (% $$ ( 9*
ISR[4] TXRDYB - Channel B Transmitter Ready
(% (" %" ($('% 9* (% & $ (%
$& '' ' ' + , ( (%
'$ , (% ' ' 9*K
$ (% % -(" ' ' (% %+$
5E (% % %( (% (((&
$ $ (% '$ %( (% $(%$
'% $$ ( 9* ( %( (%
$(%$ ( %($
@